A system memory, which is generally implemented with a Dynamic Random Access Memory (DRAM), is essential to a digital data-processing system. Reading from or writing to a DRAM is generally controlled by a memory controller of the system, e.g. a north bridge chip or chipset of a computer system. Depending on different reading/writing designs, a variety of types of DRAMs are developed, including Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), etc.
A conventional SDRAM performs data reading/writing in response to rising edges of a data-triggering signal. A DDR SDRAM, on the other hand, takes advantages of both rising and falling edges of a data-triggering signal to read/write data at a double rate. Please refer to FIG. 1, which illustrates timing sequences of a data signal DQ and a data-triggering signal (data strobe) DQS associated with a DDR memory. The data-triggering signal DQS is derived by delaying a signal DQS_0, which is generated accompanying the data signal DQ and is in phase with the data signal DQ, by a quarter of one cycle. The rising edges and falling edges of the data-triggering signal DQS thus properly locate data sections from the data signal DQ. For example, assuming that the DDR memory is operated at 400 MHz, then the frequency of the data-triggering signal DQS is 200 MHz, and the period of the data-triggering signal DQS is 5 ns (10−9 second). In other words, the duration between a rising edge and an adjacent falling edge, i.e. half a cycle, is 2.5 ns. Meanwhile, since the duration for each data section, including level transition, in the data signal DQ is also 2.5 ns (see FIG. 1), the data-triggering signal DQS resulting from the phase-shifted signal DQS_0 can always well locate the data sections. That is, data D0 is properly read at a time point T0; data D1 is properly read at a time point T1; and so on.
However, if there is a phase difference between the phase-shifted signal DQS_0 and the data signal DQ which are supposed to be in phase, the resulting data-triggering signal DQS may thus fail to locate the data sections accurately. FIG. 2 illustrates a case that the rising and falling edges of the data-triggering signal DQS only locate transitions of data. Then data cannot be accurately read. In another case as shown in FIG. 3, a data-timing shift may exist due to inherent factors like electromagnetic interference from circuit board or environment. The data-timing shift also causes failure in accurately reading data in response to the data-triggering signal DQS. The above effects become more serious when the frequency of the data signal DQ and the data-triggering signal DQS is high.
Furthermore, if the data mentioned above is some kind of program codes or if it is required for executing a program, the data-reading or data-transmitting error may adversely affect the operation of the system.